The DUT Component View in VerifStudio, shows you all the different ports in the design grouped into interface specifications. The port and the interface specifications are obtained from the IPXACT specification of the DUT. IPXACT is an IEEE standard (IEEE-1685-2014) for specification of any IP block and it includes three sections. .
- List of all the ports in the design.
- List of all the protocol interfaces - includes a list of port maps (i.e, physical port on the DUT to the logical port on the protocol interface).
- List of all the registers and memory blocks - specifications of each register including the set of fields, the access policies for each field, and the address map for the registers.
The DUT Storage View in VerifStudio, shows you all the different storage elements in the design. These are obtained from the IPXACT specification of the DUT. IPXACT is an IEEE standard (IEEE-1685-2014) for specification of any IP block and its storage elements. For each storage element in an IPXACT specification includes:
- List of fields in each storage element
- Size of each field (MSB and LSB)
- Access Policy for each field
- Address Offset for each storage element
VerifStudio enables you to create and deploy a complete working testbench extremely quickly (sometimes within a matter of minutes). The inputs needed by VerifiStudio to successfully create a UVM testbench include :
- IPXACT specification of the protocols - including bus_definition and abstraction_definition files.
- XML specification of the VIP - containing VIP specific information regarding transactions variables and configuration variables
- IPXACT specification of DUT - containing information about ports, port maps and register.
The sequence editor enables you to create UVM sequences with a simple drag-and-drop operation or with a couple of lines of Python code.
VerifStudio organizes sequences into multiple buckets.
- Basic Sequences - typically a simple VIP transaction sequence customized for a specific VIP.
- Hierarchical Sequences - a combination of multiple sequences organized
- Virtual Sequences - a set of hierarchical and simple sequences with timing constraints and target assignments.
VerifStudio generates UVM code for the entire testbench and tests including (a) tb_top, (b) uvm_env, (c) uvm_scoreboard template (d) uvm_sequences (e) uvm_tests. The main focus fo VerifStudio's code generator is "Readability". As a result, the code produced by VerifStudio is :
- well commented
- well indented
- very readable
- easily understandable
- easily debuggable
VerifStudio is integrated with a built-in Python Interpreter. This enables you to use Python to create all your UVM verification code.
- Use the powerful API in the tool to create the testbench and all components in the uvm_environment.
- Build complex UVM sequences using the python API.
- A few lines of Python can easily turn into thousands of UVM tests with different configurations thanks to the Python API built into the tool