• Slider Banner

    Introducing Verifstudio

    Fastest and easiest way to create UVM testbenches, sequences, virtual sequences and UVM tests.

    Read more
  • Slider Banner

    Improve verification productivity

    By using this automated solution for generation of UVM, your team can perform very efficiently.

    Read more
  • Slider Banner

    Meet your coverage goals faster

    The python interpreter in VerifStudio can be used create new tests that help reach coverage goals quickly.

    Read more
  • Slider Banner

    Leverage the power of Automation

    Leverage the automation provided by VerifStudio to generate correct, readable, documented UVM code.

    Read more

DVCON 2021 India Presentation

DVCON India 2021

A RISC-V Processor Verification methodology using the Portable Stimulus Standard

Loganath Ramachandran, (Accelver Systems Inc) ,

Raj Mitra, R Mahesh, Bidisha Das (Cisma Consultants, Bangalore)

RISC-V has been gaining momentum in recent years because of its open-source ISA.  Verification of
such processors is a very daunting task, because one has to ensure that 

  • all the instructions are completely verified with many possible register combinations

  • many interesting (and frequently-used) instruction-sequences need to be verified with different register combinations.

It is typical to use testcase generators, which generate a random set of instructions generated using the principles of constrained randomization. In this paper we present a novel approach for RISC-V instruction generation using a Portable Stimulus Standard (PSS) description.