DVCON 2021 India Presentation
A RISC-V Processor Verification methodology using the Portable Stimulus Standard
Loganath Ramachandran, (Accelver Systems Inc) ,
Raj Mitra, R Mahesh, Bidisha Das (Cisma Consultants, Bangalore)
RISC-V has been gaining momentum in recent years because of its open-source ISA. Verification of
such processors is a very daunting task, because one has to ensure that
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all the instructions are completely verified with many possible register combinations
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many interesting (and frequently-used) instruction-sequences need to be verified with different register combinations.
It is typical to use testcase generators, which generate a random set of instructions generated using the principles of constrained randomization. In this paper we present a novel approach for RISC-V instruction generation using a Portable Stimulus Standard (PSS) description.